This document addresses the targets of electrostatic discharge (ESD) design, manufacturing control, and testing for die-to-die (D2D) interconnects, which is exclusively a topic for IC assembly and testing of chiplets by OSATs, foundries, or IDMs. Once the chiplets are assembled in a package these die-to-die interfaces are no longer exposed to ESD risk.
- Published:
- 11/01/2023
- Number of Pages:
- 70
- File Size:
- 1 file , 4 MB
- Note:
- This product is unavailable in Russia, Belarus
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