JEDEC JESD263

This document defines a constant voltage stress (CVS) test procedure for estimating time-dependent dielectric breakdown or “wear-out” of gate dielectrics. The test is designed to obtain area, voltage and temperature acceleration parameters required to estimate dielectric lifetime at use conditions and may be applied at wafer-level or on packaged devices.
The document also describes tests designed for simplicity, speed and ease of use; generally performed at wafer level: Voltage-Ramp (V-Ramp), Tunable V-Ramp, Current-Ramp (J-Ramp) and the Constant Current (Bounded J-Ramp) tests.
The test procedures defined herein can be used for capacitor testing, but are more commonly used for testing of transistors. Transistors may be tested in inversion or accumulation, and voltage bias may be applied to the gate or drain of the transistor. Since the extrapolation parameters may be different for inversion and accumulation, the product-relevant case (e.g. transistor in inversion) should be covered.
The document describes methods to obtain voltage, temperature, area and statistical-dependence for the time to reach a given failure fraction for a constant voltage stress or a regular unipolar AC-stress. These data can be used by simulation tools which estimate the effect of irregular voltage or temperature excursions on the lifetime of a transistor or capacitor. Such simulation tools are beyond the scope of this standard.
The document includes recommended data analysis methods and guidelines for statistical sampling and analysis as well as various sources of measurement error that could affect test results.
This document includes informative annexes that discuss test structure design (A.1), breakdown detection for CVS using an increase in noise criterion (A.2), breakdown detection for V-Ramp using a change in slope of the I-V curve (A.3), a methodology to compare CVS and V-Ramp data (A.4), statistical models (A.5 and A.6), methodology for calculating overall reliability (A.7), methodology for analyzing data which does not form a single-sloped Weibull distribution (A.8), a discussion of the interdependence of voltage and temperature acceleration factors for gate dielectric breakdown time (A.9), a comparison of AC and DC stress (A.10), a method for handling a range of dielectric thicknesses which occur in a process (A.11), a discussion of voltage acceleration in the Fowler-Nordheim tunneling regime vs. the direct-tunneling regime (A.12), a discussion of SiO2 bandgap ionization by carriers with energies exceeding 9 eV (A.13), a discussion of transistor punch-through (A.14), a discussion of example failure rate calculations (B.1 through B.6), and Fowler-Nordheim and Direct-tunneling phenomena (C.1).

Published:

03/01/2024

Number of Pages:

70

File Size:

1 file , 1.7 MB

Note:

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