JEDEC JESD323

This standard defines the electrical and mechanical requirements for 288-pin, 1.1 V (VDD), Clocked, Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR5 SDRAM CUDIMMs). These DDR5 Clocked Unbuffered DIMMs (CUDIMMs) are intended for use as main memory when installed in Computers.

Reference design examples are included which provide an initial basis for DDR5 CUDIMM designs. Modifications to these reference designs may be required to meet all system timing, signal integrity and thermal requirements for PC5-6400 and beyond PC5-7200 support. All DDR5 CUDIMM implementations must use simulations and lab verification to ensure proper timing requirements and signal integrity in the design.

Published:

12/01/2023

File Size:

1 file , 930 KB

Note:

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