This standard defines concepts, terminology, and informationrequired for constructing a VHDL component model to be used in ahierarchical design and simulated interoperably with other modelsconforming to this standard.
Purpose
In order to specify and simulate a complex hardware systemconsisting of multiple components, it is necessary to define commonmodeling interfaces. conventions, and simulation modes. Commonalityassures that any new components developed for the hardware systemcan be simulated together. Commonalty also assures that newcomponents will simulate with component models obtained fromstandard libraries or reused from previous designs. The purpose ofthis specification is to provide guidelines for the production ofVHDL models for hardware descriptions that:
• conform to a common signal interface convention
• possess common simulation capabilities
• are reusable as library elements of other designs
• support multiple source procurement
• support technology independent reprocurement
It is not the purpose of this specification to create modelsthat promote a particular hardware design methodology.
- Edition:
- A
- Published:
- 07/01/1995
- ANSI:
- ANSI Approved
- Number of Pages:
- 48
- File Size:
- 1 file , 1.6 MB
Reviews
There are no reviews yet.